Circuit Simulation and Compact Modeling
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11:50 – 12:10 |
A compact physical expression for the static drain current in heterojunction barrier CNTFETs Manojkumar Annamalai and Michael Schröter Chair for Electron Devices and Integrated Circuits, Technische Universität Dresden (Germany) |
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12:10 – 12:30 |
Enabling medium thick gate oxide devices in 22FDX(r) technology for switch and high-performance amplifier application Tom Herrmann1, Alban Zaka1, Zhixing Zhao1, Binit Syamal1, Wafa Arfaoui1, Ruchil Jain1, Ming-Cheng Chang1, Sameer Jain2 and Shih Ni Ong3 1GlobalFoundries Dresden (Germany) 2GlobalFoundries Malta (Malta) 3GlobalFoundries Singapore (Singapore) |
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12:30 – 12:50 |
Non-Quasi-Static Modeling and Methodology in Fully Depleted SOI MOSFET for L-UTSOI model S. Martinie1, O. Rozeau1, HyoEun Park2, Sungjoon Park2, P. Scheer3, S.El Ghouli3, A. Juge3, H. Lee2 and T. Poiroux1 1Univ. Grenoble Alpes, CEA, LETI (France) 2Samsung (South Korea) 3STMicroelectronics (France) |
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12:50 – 13:10 |
String-level Compact Modeling Based on Channel Electrostatic Potential for Dynamic Operation of 3D Charge Trapping Flash Memories Sunghwan Cho1 and Byoungdeog Choi2 1Department of Semiconductor and Display Engineering, Sungkyunkwan University (Republic of Korea) 2Department of Electrical and Computer Engineering, Sungkyunkwan University (Republic of Korea) |