Tunneling and Steep Slope Devices
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11:50 – 12:10 |
Assessment of Lateral and Vertical Tunneling FETs Based on 2D Material for Ultra-Low Power Logic Applications Yuanchen Chu1,3, Shang-Chun Lu2,3, Michael Povolotskyi1, Gerhard Klimeck1, Umberto Ravaioli2, Tomás Palacios3 and Mohamed Mohamed4 1School of Electrical and Computer Engineering, Purdue University (USA) 2Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign (USA) 3Microsystems Technology Laboratories, MIT (USA) 4MIT Lincoln Laboratory (USA) |
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12:10 – 12:30 |
Full Quantum Simulation of Shockley-Read-Hall Recombination in p-i-n and Tunnel Diodes A. Pilotto, P. Dollfus, J. Saint-Martin, M. Pala Université Paris-Saclay, CNRS (France) |
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12:30 – 12:50 |
On the Feasibility of DoS-Engineering for Achieving Sub-60 mV Subthreshold Slope in MOSFETs J.M. Gonzalez-Medina1, Z. Stanojevic1, Z. Hou2, Q. Zhang2, W. Li2, J. Xu2 and M. Karner1 1Global TCAD Solutions (Austria) 2HiSilicon Technologies (China) |
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12:50 – 13:10 |
Theoretically probing the relationship between barrier length and resistance in Al/AlOx/Al tunnel Junctions Paul Lapham and Vihar Georgiev Device Modelling Group, James Watt School of Engineering, University of Glasgow (Scotland, United Kingdom) |