POSTER BOARDS

 
Program for: Wednesday, September 6, 2000
             Thursday, September 7, 2000
             Friday, September 8, 2000
Thursday, September 7
P-1 "Simulation of Boron Diffusion in Strained Si1-x Gex Epitaxial Layers"
K. Rajendran, W. Schoenmaker, S. Decoutere, and M. Caymax,
IMEC vzw, Leuven, Belgium
P-2 "Model for the Evolution of Dislocation Loops in Silicon"
I. Avci, H.A. Rueda*, M.E. Law,
University of Florida and *Motorola
P-3 "Prediction of SiO2 sputtering Yield Using Molecular Dynamics Simulation"
K. Lee, and T-K Kim*,
Samsung Advanced Institute of Technology and *Samsung Electronics Co.
P-4 "A Mesh Generation Algorithm for Complex Geometry"
S. Yoon, O. Kwon, S. Yoon, H. Jung, and T. Won,
Inha University, Inchun, Korea
P-5 "Optimum Node Positioning in Adaptive Grid Refinement and the Delauney-Voroni Algorithm"
C. Pladdy, and M.E. Law,
University of Florida, Gainesville, FL
P-6 "Application of an Algebraic Multigrid Solver to Process Simulation Problems"
T. Füllenbach, K. Stüben, S. Mijalkovic*,
German National Center for Information Technology and *DELFI Univeristy of Technology
P-7 "A Physics-Based Empirical Pseudopotential Model for Calculating Band Structures of Simple and Complex Semiconductors"
G. Pennington, N. Goldsman, J. McGarrity*, and F. Crowne*,
University of Maryland, College Park, MD and *Army Research Lab
P-8 "Monte Carlo Simulation of Current Fluctuation at Actual Contact"
K. Matsuzawa, N. Sano*, K. Natori*, M. Mukai**, and N. Nakayama***,
Toshiba Corporation, Yokohama, Japan, *Tsukuba University, Japan, **Sony Corporation, Japan and ***Semiconductor Technology Academic Research Center (STARC), Japan
P-9 "Simulation of Self-Heating and Contact Resistance Influences on nMOSFETs"
K. Matsuzawa, H. Kawashima*, and K. Ouchi*,
Toshiba Corporation, Yokohama, Japan and *Toshiba Corporation Semiconductor Company
P-10 "SOI Related Simulation Challenges with Moment Based BTE Solvers"
J.L. Egley, B. Polsky*, B. Min, E. Lyumkis*, O. Penzin*, and M. Foisy,
Motorola Inc., DigitalDNA Labs, Austin, TX and *Integrated Systems Engineering, San Jose, CA
P-11 "Analysis of HBT Behavior After Strong Electrothermal Stress"
V. Palankovski, S. Selberherr, R. Quay*, and R. Schultheis**,
TU Vienna, Vienna, Austria, *Fraunhofer-Institute of Applied Solid-State Physics, Freiburg, Germany and **Infineon Technologies AG, Munich, Germany
P-12 "Optimizing Free Carrier Absorption Measurements for Power Devices by Physically Rigorous Simulation"
R. Thalhammer, F. Hille, G. Wachutka,
Munich University of Technology, Munich, Germany
P-13 "A New Method to Determine Channel Mobility Model Parameters in Submicron MOSFET's using Measured S-Parameters"
S. Lee, and H.K. Yu*,
Hankuk Univiversity, Kyungki-do, Korea and *Electronics and Telecommunications Research Institute, Taejon, Korea
P-14 "Extraction of the Physical Oxide Thickness Using the Electrical Characteristics of MOS Capacitors"
K. Eikyu, H. Takashino, M. Kidera, A. Teramoto, H. Umeda, K. Ishikawa, and M. Inuishi,
Mitsubishi Electric Corporation, Hyogo, Japan
P-15 "HiSIM: A Drift-Diffusion-Based Advanced MOSFET Model for Circuit Simulation with Easy Parameter Extraction"
M. Suetake, K. Suematsu, H. Nagakura, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro*, T. Yamaguchi*, S. Odanaka*, and N. Nakayama,
Hiroshima University, Higashi-Hiroshima, Japan and *Semiconductor Technology Academic Research Center, Tokyo, Japan
P-16 "Simulation of Multiple-Bit Soft Errors Induced by Cosmic Ray Neutrons in DRAMs"
Y. Tosaka, and S. Satoh,
Fujitsu Laboratories, Ltd., Atsugi, Japan
P-17 "Guidelines for the Power Constrained Design of a CMOS Tuned LNA"
J-S Goo, K-H Oh, C-H Choi, Z. Yu, T.H. Lee, and R.W. Dutton,
Stanford University, Stanford, CA
P-18 "A High Signal Swing Pass-Transistor Logic Using Surrounding Gate Transistor"
T. Endoh, T. Funai, H. Sakuraba, and F. Masuoka,
Tohoku University, Sendai, Japan
P-19 "Development of an Optimized 40V pDMOS Device by Use of a TCAD Design of Experiment Methodology"
P. Moens, M. Tack, H.Van hove, M. Vermandel*, and D. Bolognesi,
Alcatel Microelectronics, Oudenaarde, Belgium and *University of Ghent, Belgium
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