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Conference Chair
Phil
Oldiges
IBM
Corporation
Technical Committee Chair
Karti
Mayaram
Oregon
State University
Technical Committee Members:
A. Alam, Purdue Univ.
V. Axelrad, Sequoia Design Systems
S. Banerjee, UT Austin
T. Cale, RPI
S. Chakravarthi, TI
C. Dai, Intel
S. Dunham, Univ. Washington
N. Goldsman, Univ. Maryland
T. Grasser, TU Vienna
A. Heringa, Philips Eindhoven
T. Iwasaki, Hitachi
H. Jaouen, STMicroelectronics
E. Kan, Cornell Univ.
Z. Krivokapic, AMD
J. Lorenz, Fraunhofer IISB
K. Matsuzawa, Toshiba
C. Mouli, Micron
M. Ogawa, Kobe Univ.
H. Oka, Fujitsu
M. Orlowski, Freescale
Y.-K. Park, Samsung
M. Rudan, Università di Bologna
G. Wachutka, TU Munich
Z. Yu, Tsinghua Univ.
Contact Information
Email::sispad06@gloworm.stanford.edu
Phone: (650)723-1349
Fax:(650)725-7731
www-tcad.stanford.edu/sispad06
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Under
the sponsorship of the Electron Devices Society of the IEEE, an international
conference on the numerical modeling of semiconductor devices, processes and
equipment for integrated circuits will be held in Monterey, California, USA
from September 6-8, 2006.
This meeting provides an opportunity
for the presentation and discussion of recent advances in modeling and
simulation of semiconductor devices, processes and equipment for increased
understanding and for applications to both design and manufacturing. The
program consists of 20-minute presentations, with ample time for questions
and answers. A poster session is also planned, which provides for a less
formal venue and allows for more in-depth interactions with the authors. The
presentations will be selected from two-page abstracts of topics which may
include:
- All aspects of device simulation, including transport in
nano-structures and structures using non-conventional materials, effects of
strain on carrier transport, models of device scaling limits, quantum
effects, reliability, fluctuations, and novel nano-scale devices such as QCA,
SET, and molecular devices.
- All aspects of process simulation, including both
continuum and atomistic approaches, models for dopant activation and
diffusion, oxidation, silicide growth, interface effects, and effects
due to stress.
- Equipment, topography, and lithography simulation.
- Interconnect modeling and algorithms including
noise and parasitic effects.
- Compact device modeling for circuit simulation, including
high frequency and noise modeling.
- Integration of circuit, device, process simulation
with applications to performance modeling of circuits.
- User interfaces and visualization.
- High performance computing, advanced numerical
methods and algorithms, including gridding.
- Simulations of new memory structures such as
nanocrystal, phase change, MRAM, and devices such as microsensors,
microactuators, optoelectronics devices, lasers, and flat panel
displays.
- Benchmarking, calibration, and verification of models
and simulators.
Deadline for
submission of abstracts --
Feb. 24, 2006
Two-page abstracts must be submitted by email to sispad06@gloworm.stanford.edu (PDF format only) and should include:
1. Title of Paper
2. Name, complete mailing address, and email of first author
3. Names and affiliations of additional authors
Authors will be notified of the Technical Program Committee's decision by April
28, 2006.
Companion workshop on Tuesday, Sept. 5, 2006
"Gate Stack and Contact Engineering for sub-30nm FETs"
Organizers: R. Dutton, Y. Nishi, K. Saraswat, Stanford University
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CALL
FOR PAPERS