Session 4: Stress Effects on Carrier
Transport
Location: Conference
Room New York
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14:00 |
Theoretical Analysis of Stress and Surface
Orientation Effects on Inversion Carrier Mobility
Ezaki, T., Nakamura, H.,
Yamamoto, T., Takeuchi, K., Hane, M.
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System
Devices Research Laboratories, NEC Corporation, Japan |
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14:20
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CMOS Circuit Performance Enhancement by
Surface Orientation Optimization
Chang, L., Ieong, M.,
Yang, M.
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IBM
T.
J. Watson Research Center, USA |
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14:40
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Modeling of Stress Induced Layout Effect on
Electrical Characteristics of Advanced MOSFETs
Fujii, O., Yoshimura, H.,
Hasumi, R., Sanuki, T., Oyamatsu, H., Matsuoka, F., Noguchi, T.
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Advanced
Logic Technology Department, System LSI Division I, Semiconductor
Company, Toshiba Corporation, Japan
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15:00
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Coffee Break
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15:30
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Hole Mobility Enhancement Modeling and
Scaling Study for High Performance Strained Ge Buried Channel PMOSFETs
Wang1, X.,
Shang2, H., Oldiges1, P., Rim2, K.,
Koester2, S., Ieong1, M.
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IBM
Semiconductor Research and Development Center
1 Microelectronics Division, NY
2 Research Division, IBM T.J. Watson Research
Center |
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15:50
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Three-Dimensional Characterization and
Modelling of Stress Distribution in High-Density DRAM Memory Cells
Li1, J., Hull1,
R., Yang2, R., Hou2, V., Mouli2, C.
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1
Department of Material Science and Engineering, University of Virginia,
Charlottesville
2 R&D, Micron Technology Inc, Boise
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16:10
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Strain Optimization to Reduce Gate Leakage
Current in MOS Transistors with Silicon Oxynitride Gate Dielectrics by
Use of First-Principles Calculations
Kanegae, Y., Moriya, H.,
Iwasaki, T
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Mechanical
Engineering Research Laboratory, Hitachi, Ltd., Japan |
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