Technical Program
Session 4: Advanced Circuit Modeling and Heterostructure Simulation
Session 5: AC Analysis of Device Performances
Session 6: Atomistic Modeling and Fluctuation Simulation
Session 7: Numerics and Algorithm
Session 11: Process Modeling II
Session 12: Quantum Transport Modeling
Session 1: Plenary Session (Intl.
Conference Hall)
Chairpersons: R.W. Dutton, Stanford Univ.
M. Miura-Mattausch, Hiroshima
Univ.
9:00 |
Opening
and Welcome Remarks S. Odanaka, Osaka Univ. |
9:10 1-1 |
Plenary:
What is Interesting Now and Future in Microscopic Carrier
Transport ? T. Ando Tokyo
Inst. of Technol., Japan |
9:55 1-2 |
Plenary:
Integrated TCAD and ECAD Solutions - A Paradigm Shift S.-W. Lee Intel,
USA |
10:40 1-3 |
Plenary:
Coupled-Field Modeling of Microdevices and Microsystems G. Wachutka Technische
Univ. Muenchen, Germany |
11:25 Lunch
Session 2: Physical Modeling (Intl.
Conference Hall)
Chairpersons: H. Oka, Fujitsu Labs.
P.
Oldiges, IBM
12:45 2-1 |
Surface
Mobility in Silicon at Large Operating Temperature (Invited) G. Baccarani Univ.
of Bologna, Italy |
13:20 2-2 |
Simulation
of DGSOI MOSFETs with a Schrodinger-Poisson Based Mobility Model A. Schenk and A. Wettstein* Swiss
Fed. Inst. of Technol. and *Integrated Systems Eng., Switzerland |
13:40 2-3 |
Ensemble
Monte Carlo/Molecular Dynamics Simulation of Inversion Layer Mobility in Si
MOSFETs -Effects of Substrate Impurity Y. Kamakura, H. Ryouke and K.
Taniguchi Osaka
Univ., Japan |
14:00 2-4 |
Investigation
of the Electron Mobility in Strained Si1-xGex at
High Ge Composition S. Smirnov, H. Kosina and S.
Selberherr Technical
Univ. Vienna, Austria |
14:20 Break
Session 3: TCAD Applications (Intl.
Conference Hall)
Chairpersons: Y. Oda, Matsushita
S.-W.
Lee, Intel
14:35 3-1 |
A
Strategy for Enabling Predictive TCAD in Development of Sub 100nm CMOS
Technologies (Invited) C. Machala, S. Chakravarthi,
D. Li*, S.-H. Yang and C. Chidambaram Texas
Instruments and *University of Texas, USA |
15:10 3-2 |
On
the Optimal Shape and Location of Silicided Source and Drain Contacts P. Oldiges, C. Murthy, X.
Wang, S. Fung and R. Purtell IBM,
USA |
15:30 3-3 |
GIDL
Simulation and Optimization for 0.13ƒÊm/1.5V Low Power CMOS Transistor Design S. Zhao, S. Tang, M.
Nandakumar, D.B. Scott, S. Sridhar, A. Chatterjee, Y. Kim, S.-H.
Yang, S.-C. Ai and S.P. Ashburn Texas
Instruments, USA |
15:50 3-4 |
TCAD
Driven Drain Engineering for Hot Carrier Reduction of 3.3V I/O PMOSFET N. Miura, H. Hayashi, H.
Komatsubara, M. Mochizuki and K. Fukuda Oki
Electric, Japan |
16:10 Break
Session 4: Advanced Circuit Modeling and
Heterostructure
Simulation (Intl. Conference Hall)
Chairpersons: S. Ho, Hitachi
N. Goldsman, Univ. of Maryland
16:25 4-1 |
Circuit-Simulation Model of Gate-Drain-Capacitance Changes in Small-Size MOSFETs Due to High Channel-Field Gradients D. Navarro, K. Hisamitsu, T.
Yamaoka, M. Tanaka, H. Kawano, H. Ueno, M.
Miura-Mattausch, H.J. Mattausch, S. Kumashiro*, T. Yamaguchi*,
K. Yamashita* and N. Nakayama* Hiroshima
Univ. and *STARC, Japan |
16:45 4-2 |
2D Simulation of a Buried-Heterostructure Tunable Twin-Guide DFB Laser
Diode L. Schneider, A. Witzig, A.
Bregy, B. Schmidt*, M. Streiff, M. Pfeiffer and W. Fichtner ETH
Zurich and *Nortel Networks Optical Components, Switzerland |
17:05 4-3 |
A
Comprehensive Simulation Study on Strained-Si/SiGe nMODFET Scaling for RF
Applications Q.C. Ouyang, S.J. Koester,
J.O. Chu, A. Grill, S. Subbanna and D.A. Herman Jr. IBM,
USA |
17:25 4-4 |
Realistic
Scaling Scenario for Sub-100nm Embedded SRAM Based on 3-Dimensional
Interconnect Simulation Y. Tsukamoto, T. Kunikiyo, K.
Nii, H. Makino, S. Iwade, K. Ishikawa and Y. Inoue Mitsubishi
Electric, Japan |
18:15 Reception (Reception Hall)
(Intl. Conference Hall)
Chairpersons: G. Wachutka, Technische Univ. Muenchen
C.
Diaz, TSMC
9:00 5-1 |
On
the Large-Signal CMOS Modeling and Parameter Extraction for RF Applications
(Invited) M. Je, I. Kwon, J. Han, H.
Shin and K. Lee KAIST,
Korea |
9:35 5-2 |
Drift-Diffusion-Based
Modeling of the Non-Quasistatic Small-Signal Response for RF-MOSFET Applications S. Jinbou, H. Ueno, H.
Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch and H.J.
Mattausch Hiroshima
Univ., Japan |
9:55 5-3 |
The
Physical Phenomena Responsible for Excess Noise in Short-Channel MOS Devices R. Navid and R.W. Dutton Stanford
Univ., USA |
10:15 5-4 |
Simulation
of Substrate Currents W. Schoenmaker, P. Meuris, W.
Magnus and B. Maleszka IMEC,
Belgium |
10:35 Break
Session 6: Atomistic Modeling and Fluctuation Simulation
(Intl. Conference Hall)
Chairpersons: M. Hane, NEC
S.
Dunham, Univ. of Washington
10:50 6-1 |
Multiscale
Simulation of Diffusion, Deactivation, and Segregation of Dopants
- Ab-Initio to Continuum (Invited) W. Windl Ohio
State Univ., USA |
11:25 6-2 |
Integrated
Atomistic Process and Device Simulation of Decananometre MOSFETs A. Asenov, M. Jaraiz*, S.
Roy, G. Roy, F. Adamu-Lema, A.R. Brown, V. Moroz** and R.
Gafiteanu** Univ.
of Glasgow, UK, *Univ. de Valladolid, Spain and **Avant!,
USA |
11:45 6-3 |
3D
MOSFET Simulation Considering Long-Range Coulomb Potential Effects for
Analyzing Statistical Dopant-Induced Fluctuations Associated with Atomistic
Process Simulator T. Ezaki, T. Ikezawa, A.
Notsu, K. Tanaka and M. Hane NEC,
Japan |
12:05 6-4 |
Transistor
Width Dependence of LER Degradation to CMOS Device Characteristics J. Wu, J. Chen and K. Liu Texas
Instruments, USA |
12:25 Lunch
Session 7: Numerics and Algorithm (Intl. Conference Hall)
Chairpersons: M. Kimura, Sony
P.
Leon, Mixed Technology Associates
13:40 7-1 |
Enhanced
Advancing Front Delaunay Meshing in TCAD P. Fleischmann and S. Selberherr Technical
Univ. Vienna, Austria |
14:00 7-2 |
In-Advance
CPU Time Analysis for Monte Carlo Device Simulations C. Jungemann and B.
Meinerzhagen Univ.
of Bremen, Germany |
14:20 7-3 |
An
Efficient Algorithm for 3D Interconnect Capacitance Extraction Considering
Floating Conductors O. Cueto, F. Charlet and A.
Farcy* CEA
and *STMicroelectronics, France |
14:40 Break
Session 8: MEMS and ESD (Intl. Conference Hall)
Chairpersons: T. Toyabe, Toyo Univ.
W.
Schoenmaker, IMEC
14:55 8-1 |
System
Level Model of Damping Effects for Highly Perforated Torsional Structures G. Schrag, R. Sattler and G.
Wachutka Munich
Univ. of Technol., Germany |
15:15 8-2 |
A
Novel CDM-Like Discharge Effect During Human Body Model (HBM) ESD Stress V. Axelrad, Y. Huh*, J.W.
Chen* and P. Bendix* Sequoia
Design Systems and *LSI Logic, USA |
15:35 8-3 |
Simulation
Technique of Heating by Contact Resistance for ESD Protection Device K. Matsuzawa, H. Kawashima,
T. Matsuhashi and S. Yasuda Toshiba,
Japan |
16:15-18:15 Poster Session (Room 401, 4F)
P-1 Atomistic Simulation of RTA Annealing for
Shallow
Junction
Formation Characterizing both BED and TED
M.
Yu, R. Huang, X. Zhang, Y. Wang and H. Oka*
Peking Univ., China and *Fujitsu Labs.,
Japan
P-2 Direct Tunneling Gate Current in Deep Sub-Micron
MOSFETs
in the Presence of Inelastic Scattering
A.
Haque, K. Alam and S. Zaman
Bangladesh Univ. of Eng. and Technol.,
Bangladesh
P-3 Three-Dimensional Triangle-Based Simulation
of Etching Processes
O.
Lenhart and E. Bar
Fraunhofer Inst. of Integrated Circuits,
Germany
P-4 Automatic Order Reduction of
Thermo-Electric Model for
Microthrusters
Ignition Unit
T.
Bechtold, E.B. Rudnyi and J.G. Korvink
Univ. of Freiburg, Germany
P-5 Numerical Modeling of Silicon Film
Deposition in Very-
High-Frequency
Plasma Reactor
K.
Satake, Y. Kobayashi and S. Morita
Mitsubishi Heavy Inds., Japan
P-6 Gate Tunnelling and Impact Ionisation in
Sub 100nm PHEMTs
K.
Kalna and A. Asenov
Univ. of Glasgow, UK
P-7 Extraction of 3D Interconnect Impedances
Using Edge
Elements
without Gauge Condition
E.
Charlet and J.F. Carpentier*
CEA and *STMicroelectronics, France
P-8
Impact
of Electron Heat Conductivity on Electron Energy Flux
K.
Matsuzawa
Toshiba, Japan
P-9
Analysis
of the Effects of Scaling on Thermal Noise in MOSFETs
S.
Spedo and C. Fiegna
Univ. of Ferrara, Italy
P-10 Modeling of Ultra Shallow
Junctions and Hybrid
Source/Drain
Profiles Annealed by Soak and Spike RTA
C.C.
Wang, C.S. Chang, P. Griffin* and C.H. Diaz
TSMC, Taiwan and *Stanford Univ., USA
P-11 Investigation of Magnetic Field
Effects on Energy Gap for
Nanoscale
InAs/GaAs Semiconductor Ring Structures
Y.
Li, O. Voskoboynikov*, H.-M. Lu**, C.P. Lee* and
S.M.
Sze
National Nano Device Labs., *National Chiao
Tung Univ. and
**National
Tsing Hua Univ., Taiwan
P-12 Self-Consistent Single-Particle
Simulation
F.M.
Bufler, C. Zechner*, A. Schenk and W. Fichtner
ETH Zurich and *Integrated Systems Eng.,
Switzerland
P-13 Nanoelectronic 3-D (NEMO 3-D)
Simulation of
Multimillion
Atom Quantum Dot Systems
F.
Oyafuso, G. Klimeck, R.C. Bowen and T.B. Boykin*
California Inst. of Technol. and *Univ. of
Alabama at
Huntsville,
USA
P-14 Characterization of Multi-Barrier
Tunneling Diodes and
Vertical
Transistors Using 2-D Device Simulation
K.-D.
Kim, K.-H. Lee, S.-J. Baik, T.-K. Kim and J.-T. Kong
Samsung Electronics, Korea
P-15 Hot-Carrier Energy Distribution
Model and Its
Application
to the MOSFET Substrate Current
C.
Lee, G. Jin, K. Lee, J. Kong, W. Lee, Y. Roh*, E.C. Kan**
and
R.W. Dutton***
Samsung Electronics, *Sungkyunkwan Univ.,
Korea,
**Cornell
Univ. and ***Stanford Univ., USA
P-16 Numerical Simulation of
Two-Particle Wave Function in Quantum Wires
S.
Reggiani, A. Bertoni and M. Rudan
Univ. of Bologna, Italy
P-17 Cross Validation of Quantum Simulations
and Optical
Measurements
in Single Electron Memories with Silicon
Nano-Crystallites
A.
Poncet, C. Busseret and A. Souifi
INSA-Lyon, France
P-18 A Strategy to Enforce the Discrete
Minimax Principle on
Finite-Element
Meshes
T.
Binder, H. Ceric, A. Hossinger and S. Selberherr
Technical Univ. Vienna, Austria
P-19 Wigner Transport through Tunneling
Structures - a
Scattering
Interpretation of the Potential Operator
M.
Nedjalkov, R. Kosik, H. Kosina and S. Selberherr
Technical Univ. Vienna, Asutria
P-20 Simulation and Inverse Modeling of
TEOS Deposition
Processes
Using a Fast Level Set Method
C.
Heitzinger, J. Fugger*, O. Haeberlen* and S. Selberherr
Technical Univ. Vienna and *Infineon
Technols., Asutria
P-21 Simulation of a "Well
Tempered" SOI MOSFET Using
and
Enhanced Hydrodynamic Transport Model
M.
Gritsch, H. Kosina, T. Grasser and S. Selberherr
Technical Univ. Vienna, Austria
P-22 Statistical Fluctuation Analysis
by Monte Carlo Ion Implantation Method
Y.
Oda, Y. Ohkura, K. Suzuki, S. Ito, H. Amakawa and
K.
Nishi
Selete, Japan
P-23 Bias-Dependent Drift Resistance
Modeling for Accurate
DC
and AC Simulation of Asymmetric HV-MOSFET
N.
Hefyene, E. Vestiel*, S. Frere*, C. Anghel, A.M. Ionescu
and
R. Gillon**
Swiss Federal Inst. of Technol., Switzerland
and *Alcatel
Microelectronics,
Belgium
P-24 A New Non-Pair Diffusion Based Dopant
Pile-Up Model
for
Process Designers and Its Prediction Accuracy
H.
Hayashi, N. Miura, H. Komatsubara, M. Mochizuki and
K.
Fukuda
Oki Electric, Japan
18:30-20:30 Panel Discussion (Intl. Conference Room)
"What
Can Computer Aided Engineering Do for the SoC Era ?"
Moderators: H. Masuda, STARC
M. Orlowski, Motorola
Panelists:
R.W. Dutton, Stanford Univ.
M. Fukuma, NEC
S.-W. Lee, Intel
W. Schoenmaker, IMEC
S. Selberherr, Wien Inst. Tech.
T. Wada, Toshiba
TCAD
has contributed to process/device design and prediction of the device performances
for decades. This role is still very
important in very deep submicron process; however, new aspect in the
semiconductor industry has arisen.
Interconnect
issue becomes more critical in SoC timing closure. ITRS roadmap predicts future of process/devices and
interconnects, which lead to a standardized process and device. TCAD seems to be requested to contribute in the
new situation of SoC era.
The
panel addresses topics such as:
What
is the new role of TCAD in SoC era? How
TCAD can contribute towards the ultimate-solution in timing closure problem.
How
to attack SI(Signal Integrity) Physical Design by TCAD.
Can
TCAD make innovation on Process & Device, which changes the ITRS2001?
Friday, September 6
Session 9: Process Modeling I (Intl. Conference Hall)
Chairpersons: S. Ito, Toshiba
D.
Tsoukalas, NCSR 'Demokritos'
9:00 9-1 |
The
Process Modeling Hierarchy: Connecting Atomistic Calculations to Nanoscale
Behavior (Invited) S. Dunham Univ.
of Washington, USA |
9:35 9-2 |
Monte
Carlo Simulation of Consecutive Implants into SiO2 Capped Si D. Li, S.-H. Yang*, C.
Machala*, L. Lin, S.K. Banerjee, A.F. Tasch, B. Hornung* and
A. Li-Fatou* Univ.
of Texas and *Texas Instruments, USA |
9:55 9-3 |
Modeling
of Boron Diffusion in Strained Si/Si1-xGex H. Zhu, K. Lee, O. Dokumaci,
P. Ronsheim, F. Cardone, S. Hegde, U. Mantz and P.
Saunders IBM,
USA |
10:15 Break
Session 10: Device Modeling (Intl. Conference Hall)
Chairpersons: K. Fukuda, Oki
K.
DeMeyer, IMEC
10:30 10-1 |
Technology
Modeling for Emerging SOI Devices (Invited) M. Ieong and P. Oldiges IBM,
USA |
11:05 10-2 |
MOSFET
Hot-Carrier Induced Gate Current Simulation by Self-Consistent Silicon/Oxide
Monte Carlo Device Simulation A. Ghetti STMicroelectronics,
Italy |
11:25 10-3 |
A
New Gate Current Model Accounting for a Non-Maxwellian Electron Energy
Distribution Function A. Gehring, T. Grasser, H.
Kosina and S. Selberherr Technical
Univ. Vienna, Asutria |
11:45 10-4 |
Analysis
of Injection Current with Electron Temperature for High-K
Gate Stacks Y. Ohkura, H. Takashino, S.
Wakahara and K. Nishi Selete,
Japan |
12:05 10-5 |
Hot
Carrier Induced Degradation due to Multi-Phonon Mechanism Analyzed by Lattice
and Device Monte Carlo Coupled Simulation S. Ho, Y. Ohkura*, M. Takuya, J. Prasad**, N. Nakamura*** and S. Kubo*** Hitachi,
*Selete, **TATA, ELXSI and ***Hitachi ULSI Systems,
Japan |
12:25 Lunch
Session 11: Process Modeling II (Intl. Conference Hall)
Chairpersons: K. Nishi, Selete
M.
Orlowski, Motorola
13:40 11-1 |
Finite Element Analysis of Stress Evolution in Si based Front and Back Ends Micro Structures (Invited) V. Senez, A. Armigliato*, G. Carlotti**, G. Carnevale***, H. Jaouen***
and I. de Wolf**** |
14:15 11-2 |
An
Adaptive Grid Approach for the Simulation of Electromigration Induced Void
Migration H. Ceric and S. Selberherr Technical
Univ. Vienna, Austria |
14:35 11-3 |
A
New SP(Simultaneous Polishing) Model for Copper CMP Process T. Ohta and K. Suzuki Selete,
Japan |
14:55 Break
Session 12: Quantum Transport Modeling
(Intl. Conference Hall)
Chairpersons: K. Ishikawa, Mitsubishi
G.
Baccarani, Univ. of Bologna
15:10 12-1 |
Quantum
Transport Modeling in Nano-Scale Devices (Invited) M. Ogawa, H. Tsuchiya and T.
Miyoshi Kobe
Univ., Japan |
15:45 12-2 |
Simulation
of Direct Source-to-Drain Tunnelling Using the Density Gradient Formalism:
Non-Equilibrium Green's Function Calibration J.R. Watling, A.R. Brown, A.
Asenov, A. Svizhenko* and M.P. Anantram* Univ.
of Glasgow, UK and *NASA, USA |
16:05 12-3 |
Simulations
of Ultrathin, Ultrashort DG MOSFETs with the Density Gradient Transport Model E. Lyumkis, R. Mickevicius,
O. Penzin, B. Polsky, K.E. Sayed, A. Wettstein and
W. Fichtner Integrated
Systems Engineering, USA |
16:25 12-4 |
On
Density-Gradient Modeling of Tunneling through Insulators T. Hohr, A. Schenk, A.
Wettstein* and W. Fichtner ETH
Zurich and *Integrated Systems Eng., Switzerland |
16:45 12-5 |
Monte
Calro Simulation of Electron Transport in a Carbon Nanotube G. Pennington and N. Goldsman Univ.
of Maryland, USA |